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| c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . 2 0 w s t e r e o d i g i t a l c l a s s - d a u d i o p o w e r a m p l i f i e r w i t h e q a n d d r c a p a 3 1 6 0 t h e a p a 3 1 6 0 i s a d i g i t a l i n p u t , s t e r e o , h i g h e f f i c i e n c y , c l a s s - d a u d i o a m p l i f i e r a v a i l a b l e i n a t q f p 7 x 7 - 4 8 p p a c k a g e . t h e a p a 3 1 6 0 a c c e p t s t h e d i g i t a l s e r i a l a u d i o d a t a a n d u s i n g t h e d i g i t a l a u d i o p r o c e s s o r t o c o n v e r t t h e a u d i o d a t a b e c o m e s t h e s t e r e o c l a s s - d o u t p u t s p e a k e r a m p l i f i e r . t h i s p r o v i d e s t h e s e a m l e s s i n t e g r a t i o n b e t w e e n t h e c o d e c a n d t h e s p e a k e r a m p l i f i e r . t h e a p a 3 1 6 0 i s a s l a v e d e v i c e r e c e i v i n g c l o c k s f r o m e x - t e r n a l s o u r c e , a n d t h e c l a s s - d ? s p w m s w i t c h i n g f r e - q u e n c y i s 3 5 2 . 8 k h z f o r t h e s a m p l i n g r a t e 4 4 . 1 k h z o r 3 8 4 k h z f o r s a m p l i n g 4 8 k h z , d e p e n d o n t h e i n p u t s i g n a l ? s s a m p l i n g r a t e . o p e r a t i n g v o l t a g e : 8 . 0 v ~ 2 4 v f o r p v d d ? 3 . 0 v ~ 3 . 6 v f o r d v d d a n d a v d d h i g h e f f i c i e n c y c l a s s - d o p e r a t i o n e l i m i n a t e t h e n e e d o f h e a t s i n k s d i g i t a l s e r i a l a u d i o i n p u t ( s t e r e o o u t p u t ) i 2 c c o n t r o l i n t e r f a c e s a m p l i n g r a t e c a n s u p p o r t f r o m 3 2 k h z t o 1 9 2 k h z s e p a r a t e d v o l u m e c o n t r o l f r o m 2 4 d b t o m u t e s o f t m u t e ( 5 0 % d u t y c y c l e ) p r o g r a m m a b l e d y n a m i c r a n g e c o m p r e s s i o n ? p o w e r l i m i t e r ? s p e a k e r p r o t e c t i o n ? n i g h t - m o d e l i s t e n i n g p r o g r a m m a b l e b i q u a d s f o r s p e a k e r e q s h u t d o w n a n d m u t e f u n c t i o n t h e r m a l a n d o v e r - c u r r e n t p r o t e c t i o n s w i t h a u t o - r e c o v e r y s p a c e s a v i n g p a c k a g e t q f p 7 x 7 - 4 8 p l e a d f r e e a n d g r e e n d e v i c e s a v a i l a b l e ( r o h s c o m p l i a n t ) f e a t u r e s g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s l c d t v p i n c o n f i g u r a t i o n apa3160 left channel speaker right channel speaker out_a out_c out_b out_d digital audio source i 2 c control sda scl mclk lrclk sclk sdin s i m p l i f i e d a p p l i c a t i o n c i r c u i t tqfp7x7-48p (top view) apa3160 4 6 o u t _ b 4 5 p v d d _ b 4 0 p v d d _ c 4 7 p g n d _ a b 4 4 p v d d _ b 3 9 o u t _ c 4 8 p g n d _ a b 3 7 p g n d _ c d 4 3 b b s 4 2 c b s 3 8 p g n d _ c d 4 1 p v d d _ c 33 dbs 28 dvss 35 pvdd_d 32 gdreg 27 dvdd 34 pvdd_d 36 out_d 25 rst 31 dvreg 30 agnd 26 tp3 29 gnd s c l k 2 1 t p 1 1 6 s d a 2 3 l r c l k 2 0 m c l k 1 5 s d i n 2 2 s c l 2 4 a v d d 1 3 s d 1 9 2 v 5 _ d v 1 8 e r r o r 1 4 t p 2 1 7 abs 4 avss 9 tm2 8 pll_lf 10 avss 11 gdreg 5 nc 6 pvdd_a 2 pvdd_a 3 tm1 7 2v5_av 12 out_a 1
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 a p a 3 1 6 0 symbol parameter rating unit supply voltage (pvdd_x to pgnd_xx) - 0.3 to 26 supply voltage (dvdd to dvss) - 0.3 to 3.6 supply voltage (avdd to avss) - 0.3 to 3.6 input voltage (mclk to avss) - 0. 5 to avdd+2.5 input voltage (sd, rst, lrclk, sc lk, sdin, sda, scl to dvss) - 0. 5 to dvdd+2.5 input voltage (out_x to pgnd_xx) - 0.3 to +32 input voltage (xbs to pgnd_xx) - 0.3 to +43 input voltage (avss, dvss, agnd to pgnd_xx) - 0.3 to +0.3 v t j maximum junction temperature 150 o c t stg storage t emperature range - 65 to +150 o c t s dr soldering temperature range , 10 seconds 260 o c p d power dissipation internally limited w o r d e r i n g a n d m a r k i n g i n f o r m a t i o n a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . apa3160 handling code temp erature range package code package code qca : tqfp7x7-48p operating ambient tem p erature range i : -40 to 85 o c handling code tr : tape & reel a s s e m b l y m a t e rial g : halogen and lead free device apa3160 qca : apa3160 xxxxx xxxxx - date code assembly material symbol parameter typical value unit q ja junction - to - ambient resistance in f ree a ir (note 2) tqfp7x7 - 4 8 p 25 c/w q jc junction - to - case resistance in f ree a ir (note 3) tqfp7x7 - 4 8 p - c/w t h e r m a l c h a r a c t e r i s t i c s note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. the exposed pad of tqfp7x7-48p is soldered directly on the pcb. note 3: the case temperature is measured at the center of the exposed pad on the underside of the tqfp7x7-48p package. c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 a p a 3 1 6 0 range symbol parameter min. max. unit v dd supply voltage 3 3.6 pv dd full bridge stage supply voltage (pvdd_x) 8 24 v ih high l evel t hreshold v oltage sd , mclk, lrclk, sclk, sdin, sda, scl, rst 2 5 v il low l evel t hreshold v oltage sd , mclk, lr clk, sclk, sdin, sda, scl, rst 0 1 v t a ambient t emperature range - 40 85 t j junction temperature range - 40 125 o c r l speaker resistance 6 - w l o output low pass filter inductance 10 - m h r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s p w m o p e r a t i n g c o n d i t i o n s p l l i n p u t p a r a m e t e r s a n d e x t e r n a l f i l t e r c o m p o n e n t s apa3160 symbol parameter test condition s min. typ. max. unit f mclk mclk frequency 2.8224 - 24.576 m hz mclk duty cycle 40 50 60 % tr/tf (mclk) rise/fall time for mclk - - 5 ns lrclk allowable drift before lrclk reset - - 4 mclks external pll filter capacitor c1 smd 0603 y5v - 47 - external pll filter capacitor c2 smd 0603 y5v - 4.7 - nf external pll filter resistor r - 470 - w e l e c t r i c a l c h a r a c t e r i s t i c s t a = 2 5 o c , p v d d = 1 8 v , v d d = 3 . 3 v ( a v d d a n d d v d d ) , r l = 8 w , b d m o d e , f s = 4 8 k h z ( u n l e s s o t h e r w i s e n o t e d ) apa3160 symbol parameter test condition s min. typ. max. unit dc characteristics normal mode (no load) - 10 20 i dd 3.3v supply current (avdd, dvdd) reset (no load) - 7.2 14.5 normal mode (n o load) - 18 36 i pvdd full bridge stage supply curren t (pvdd_x) reset (no load) - 0.5 1 ma i il low level input current v i c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 5 a p a 3 1 6 0 s e r i a l a u d i o p o r t s s l a v e m o d e apa3160 symbol parameter test condition s min. typ. max. unit t setup2 setup time, sdin to sclk rising edge 10 - - t hold hold time, sdin to sclk rising edge 10 - - ns lrclk frequency 8k 48k 48k khz lrclk duty cycle 40 50 60 sclk duty cycl e 40 50 60 % sclk rising edges between lrclk riding edges 32 - 64 sclk edges t (edge) lrclk clock edge with respect to the falling edge of sclk - 1/4 - 1/4 sclk period tr/tf (sclk/lrclk) rise/fall time for sclk/lrclk - - 8 ns o v e r r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( u n l e s s o t h e r w i s e n o t e d ) r e s e t t i m i n g c o n t r o l s i g n a l p a r a m e t e r s o v e r r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( u n l e s s o t h e r w i s e n o t e d ) . p l e a s e r e f e r t o ? r e c - o m m e n d e d u s e m o d e l ? s e c t i o n o n u s a g e o f a l l t e r m i n a l s . apa3160 symbol parameter test condition s min. typ. max. unit t p(rst) pulse duration, rst active. no load 100 - - m s t d(12c_ready) time to enable i 2 c - - 13.5 ms i 2 c s e r i a l c o n t r o l p o r t o p e r a t i o n t i m i n g c h a r a c t e r i s t i c s f o r i 2 c i n t e r f a c e s i g n a l s o v e r r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( u n l e s s o t h e r w i s e n o t e d ) apa3160 symbol parameter test condition s min. typ. max. unit f scl frequency, scl no wait states - - 400 khz t w(h) pulse duration, scl high 0.6 - - t w(l) pulse duration, scl low 1.3 - - m s t r rise time, scl and sda - - 300 t f fall time, sc l and sda - - 300 t setup1 setup time, scl to sda 100 - - t hold1 hold time, scl to sda 0 - - ns t (buf) bus free time between stop and start condition 1.3 - - t setup2 setup time, scl to start condition 0.6 - - t hold2 hold time, start condition to scl 0.6 - - t setup3 setup time, scl to stop condition 0.6 - - m s c l load capacitance for each bus line - - 400 pf c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 6 a p a 3 1 6 0 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s e f f i c i e n c y v s . o u t p u t p o w e r ( 8 w ) 0 10 20 30 40 50 60 70 80 90 100 0 3 6 9 12 15 18 e f f i c i e n c y ( % ) output power (w) r l =8 w +33 m h f in =1khz thd+n ?? 10% aux-0025 aes-17(20khz) t h d + n v s . o u t p u t p o w e r 0.5 50 1 10 v dd =12v t h d + n ( % ) output power (w ) v dd =8v v dd =18v v dd =24v f in =1khz r l =8 w aux-0025 aes-17(20khz) 0.01 30 0.1 1 10 t h d + n v s . f r e q u e n c y 20 20k 100 1k 10k frequency (hz ) t h d + n ( % ) v dd =12v r l =8 w aux-0025 aes-17(20khz) p o =5w p o =1w 0.02 1 0.1 t h d + n v s . f r e q u e n c y c r o s s t a l k v s . f r e q u e n c y c r o s s t a l k v s . f r e q u e n c y 20 20k 100 1k 10k c r o s s t a l k ( d b ) frequency (hz ) v dd =18v p o =1w r l =8 w aux-0025 aes-17(20khz) r-ch to l-ch l-ch to r-ch -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k 100 1k 10k frequency (hz ) c r o s s t a l k ( d b ) v dd =12v p o =1w r l =8 w aux-0025 aes-17(20khz) r-ch to l-ch l-ch to r-ch -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k 100 1k 10k t h d + n ( % ) frequency (hz ) p o =5w p o =1w p o =10w v dd =18v r l =8 w aux-0025 aes-17(20khz) 0.02 1 0.1 c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 7 a p a 3 1 6 0 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) o u t p u t n o i s e v o l t a g e v s . f r e q u e n c y o u t p u t n o i s e v o l t a g e v s . f r e q u e n c y m u t e a t t e n u a t i o n v s . f r e q u e n c y s h u t d o w n a t t e n u a t i o n v s . f r e q u e n c y 20 20k 100 1k 10k g a i n ( d b ) frequency (hz ) v dd =18v r l =8 w v o =1vrms aux-0025 aes-17(20khz) right channel left channel -120 -60 -110 -100 -90 -80 -70 20 20k 100 1k 10k v dd =18v r l =8 w v o =1vrms aux-0025 aes-17(20khz) g a i n ( d b ) frequency (hz ) right channel left channel -120 -60 -110 -100 -90 -80 -70 p s r r v s . f r e q u e n c y 20 20k 100 1k 10k frequency (hz ) o u t p u t n o i s e v o l t a g e ( v r m s ) v dd =12v r l =8 w input ac ground aux-0025 aes-17(20khz) a v =10db a v =6db a v =0db 500 m 100 m 200 m 300 m 400 m 0 m 20 20k 100 1k 10k frequency (hz ) o u t p u t n o i s e v o l t a g e ( v r m s ) v dd =18v r l =8 w input ac ground aux-0025 aes-17(20khz) a v =10db a v =6db a v =0db 500 m 100 m 200 m 300 m 400 m 0 m 20 20k 100 1k 10k frequency (hz ) p s r r ( d b ) v dd =18v r l =8 w a v =20db v rr =0.2vrms input floating aux-0025 aes-17(20khz) gain =10db gain =0db gain =-10db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 8 a p a 3 1 6 0 pin no. name i/o/p function 1 out_a o output of half bridge a. 2, 3 pvdd_a p power supply for half bridge a. 4 abs i/o high side bootstrap supply for half bridge a . 5, 32 gdreg o/p internal regulator output of gate driver. 6 nc - no connection . 7 tm1 i test mode digital input pin. 8 tm2 i test mode digital input pin. 9, 11 avss p analog power supply ? s ground. 10 pll_lf o pll negative loop filter pin. 12 2v5_av o/p internal regulated 2.5v for analog block ? s supply, not for power external devi ce. 13 avdd p analog powers supply and connects to 3.3v. 14 error o when over temperature, over current over voltage and under voltage occur, this pin will be pull low; and it will be reset to high when the fault condition has be remove. 15 mclk i mast er clock input. 16 tp1 i/o test mode digital input/output pin. 17 tp2 i/o test mode digital input/output pin. 18 2v5_dv o/p internal regulated 2.5v for digital block ? s supply, not for power external device. 19 sd i active low, shutting down the noise shaper and initiating pwm stop sequence. 20 lrclk i input serial audio data left/right clock. (sample rate clock ), it ? s weak pull down terminal. 21 sclk i serial audio data clock (shift clock). sclk is the serial audio port input data bit clock. 22 sdin i serial audio data input. 23 sda io i 2 c serial control data interface input/output. 24 scl i i 2 c serial control clock input. 25 rst i reset control, place a logic low to this pin, will reset the apa3160 to its default condition. it ? s weak pull - up te rminal. 26 tp3 i/o test mode digital input/output pin. 27 dvdd p digital powers supply and connects to 3.3v. 28 dvss p digital power supply ? s ground. 29 gnd p power stage ? s analog ground. 30 agnd p power stage ? s analog ground. 31 dvreg o/p digital vo ltage regulator ? s output, only for internal used. 33 dbs i/o high side bootstrap supply for half bridge d . 34, 35 pvdd_d p power supply for half bridge d. 36 out_d o output of half bridge d. 37, 38 pgnd_cd p power ground connection for half bridge c an d d. 39 out_c o output of half bridge c. 40, 41 pvdd_c p power supply for half bridge c. 42 cbs i/o high side bootstrap supply for half bridge c. 43 bbs i/o high side bootstrap supply for half bridge b. p i n d e s c r i p t i o n c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 9 a p a 3 1 6 0 pin no. name i/o/p function 44, 45 pvdd_b p power supply for half bridge b. 46 out_b o output of half bridge b. 47, 48 pgnd_ab p power ground connection for half bridge a and b. p i n d e s c r i p t i o n ( c o n t . ) b l o c k d i a g r a m serial audio port inter polarization full bridge fet output pvdd_a out_a abs pgnd_ab lrclk pwm sdin pll_lf avdd sda dvdd eq 7xbq sampling rate serial control regulator 3.3v to 2.5v noise shaper scl pll central control mclk sclk pvdd_b pvdd_c pvdd_d out_b out_c out_d bbs cbs dbs pgnd_cd pwm drc & volume eq 7xbq register bank regulator 3.3v to 2.5v full bridge fet output control logic gate driver regulator gdreg 2v5_av 2v5_dv avss error rst sd dvss agnd c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 0 a p a 3 1 6 0 t y p i c a l a p p l i c a t i o n c i r c u i t 4 a b s 9 a v s s 8 1 0 p l l _ l f 1 1 a v s s 5 g d r e g 6 n c 2 p v d d _ a 3 p v d d _ a 7 t m 1 1 2 2 v 5 _ a v 4 6 o u t _ b s c l k 2 1 t p 1 1 6 s d a 2 3 l r c l k 2 0 m c l k 1 5 s d i n 2 2 s c l 2 4 a v d d 1 3 s d 1 9 2 v 5 _ d v 1 8 e r r o r 1 4 t p 2 1 7 1 o u t _ a 4 5 p v d d _ b 4 0 p v d d _ c 4 7 p g n d _ a b 4 4 p v d d _ b 3 9 o u t _ c 4 8 p g n d _ a b 3 7 g n d _ c d 4 3 b b s 4 2 c b s 3 8 g n d _ c d 4 1 p v d d _ c d b s 3 3 d v s s 2 8 p v d d _ d 3 5 g d r e g 3 2 d v d d 2 7 p v d d _ d 3 4 o u t _ d 3 6 d v r e g 3 1 a g n d 3 0 t p 3 2 6 g n d 2 9 r s t 2 5 0.1 m f 8 w m f 22 m h 22 m h m f 8 w m f 22 m h 22 m h m f 0.033 m f 0.033 m f 0.1 m f 220 m f v dd 0.1 m f 220 m f v dd 0.1 m f 0.033 m f 0.033 m f 1 m f 1 m f 0.1 m f dv dd 0.1 m f reset 0.047 m f 470 w 4700 p f av dd 4.7 m f 0.1 m f 10k w 18.2k w 10k w 2 2 . 1 k w scl av dd error flag master clock pdn lrck sclk sdin 0.047 m f 470 w 4700 p f apa3160 sda 0 w 10 m f 0.1 m f 10 m f v dd t m 2 0.68 0.68 0.68 0.68 c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 1 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n clock and pll the apa3160 is a slave device and receives signals from mclk, sclk, and lrclk. the digital audio processor (dap) provides all sample rates and mclk rates which defined in the clock control register. the apa3160 checks to verify that sclk is a particular value of 32f s , 48f s , or 64f s . the dap only provides a 1f s lrclk. the timing relationship of these clocks to sdin is shown in subsequent sections. serial data interface serial data is an input transmitted to sdin. the pwm outputs are derived from sdin. besides, the apa3160 dap receives left-justified, right-justified, and i 2 s serial data formats with 16, 20, or 24 bit. pwm section the apa3160 dap device is a high power efficiency and high-performance digital audio reproduction. a noise shaper is used to increase dynamic range and snr in the audio band. the pwm section receives 24bit pcm data from the dap and outputs two btl pwm audio output channels. the pwm section has individual channel dc blocking filters that can be enabled and disabled. the low pass filter cutoff frequency is less than 1hz. besides, the pwm section includes individual channel de-emphasis filters for 44.1 and 48 khz and can be enabled and disabled. the adjustable maximum modulation limit of pwm section is from 93.8% to 98.4%. i 2 c compatible serial control interface the apa3160 dap receives commands from a system controller through an i 2 c serial control slave interface. the serial control interface supports both normal-speed 100khz and high-speed 400khz operations without waiting states. as an added feature, even though the mclk is absent, the interface operates. for status registers, the serial control interface provides both single-byte and multi-byte read and write operations; and for the general control registers, they associated with the pwm. c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 2 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r e 1 . i 2 s 6 4 f s f o r m a t f i g u r e 2 . i 2 s 4 8 f s f o r m a t 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 32 clks 32 clks lrclk (note reversed phase) left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 24-bit mode 20-bit mode 16-bit mode 15 14 12 11 9 8 5 4 1 6 c l k s 16clks lrclk (note reversed phase) left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 f i g u r e 3 . i 2 s 3 2 f s f o r m a t serial interface control and timing i 2 s t i m i n g i 2 s timing uses lrclk to define the data for the left channel and the right channel when the data being transmitted. for the left channel, the lrclk is low; for the right channel, the lrclk is high. a bit clock running at 32, 48, or 64 f s is used to clock in the data. when the lrclk signal changes state, there is a delay of one bit clock from the time which the first bit of data on the data lines. the data is written msb first and is valid on the rising edge of bit clock. the dap masks unused trailing data bit positions. 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 2 4 c l k s 24 clks lrclk (note reversed phase) left channel right channel sclk sclk msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 0 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 msb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 3 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) left-justified left-justified (lj) timing uses lrclk to define the data for the left channel and the right channel when the data being transmitted. for the left channel, the lrclk is high; for the right channel, the lrclk is low. a bit clock running at 32, 48, or 64 f s is used to clock in the data. the first bit of data appears on the data lines when lrclk toggles. the data is written msb first and is valid on the rising edge of the bit clock. the dap masks unused trailing data bit positions. f i g u r e 4 . l e f t - j u s t i f i e d 6 4 f s f o r m a t f i g u r e 5 . l e f t - j u s t i f i e d 4 8 f s f o r m a t f i g u r e 6 . l e f t - j u s t i f i e d 3 2 f s f o r m a t 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 32clks 32clks lrclk left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 24-bit mode 20-bit mode 16-bit mode 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 2 4 c l k s 24 clks lrclk left channel right channel sclk sclk msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 0 23 22 17 16 9 8 5 4 19 18 13 12 5 4 15 14 9 8 msb 24-bit mode 20-bit mode 16-bit mode 1 0 1 0 3 2 1 15 14 12 11 9 8 5 4 1 6 c l k s 16clks lrclk left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 0 c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 4 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) right-justified right-justified (rj) timing uses lrclk to define the data for the left channel and the right channel when the data being transmitted. for the left channel, the lrclk is high; for the right channel, the lrclk low. a bit clock running at 32, 48, or 64 f s is used to clock in the data. after lrclk toggles, for 24bit data, the first bit of data appears on the data 8 bit-clock. in rj mode, the lsb of data is always clocked by the last bit clock before lrclk transitions. the data is written msb first and is valid on the rising edge of bit clock. the dap masks unused leading data bit positions. f i g u r e 7 . r i g h t - j u s t i f i e d 6 4 f s f o r m a t f i g u r e 8 . r i g h t - j u s t i f i e d 4 8 f s f o r m a t f i g u r e 9 . r i g h t - j u s t i f i e d 3 2 f s f o r m a t 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 32 clks 32 clks lrclk left channel right channel sclk sclk msb msb lsb lsb 24-bit mode 20-bit mode 16-bit mode 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 24-bit mode 20-bit mode 16-bit mode 23 22 19 18 15 14 1 0 19 18 15 14 1 0 1 0 24 clks 24 clks lrclk left channel right channel sclk sclk msb msb ls b ls b 24-bit mode 20-bit mode 16-bit mode 24-bit mode 6 5 2 6 5 2 15 14 6 5 2 23 22 19 18 15 14 1 0 19 18 15 14 1 0 1 0 20-bit mode 16-bit mode 6 5 2 6 5 2 15 14 6 5 2 15 14 12 11 9 8 5 4 1 6 c l k s 16clks lrclk left channel right channel sclk sclk msb lsb lsb 16-bit mode 3 2 1 0 msb 16-bit mode 13 10 15 14 12 11 9 8 5 4 3 2 1 13 10 0 c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 5 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) i 2 c serial control interface the apa3160 dap has a bidirectional i 2 c interface that compatible with the i 2 c (inter ic) bus protocol. besides, it provides both 100khz and 400khz data transfer rates to single and multiple bytes write and read operations. this is a slave only device, and it doesn?t support a multi-master bus environment or wait state insertion. the function of the control interface is to read device status and to program the registers of the device. the dap supports the standard-mode i 2 c bus operation (100khz maximum) and the fast i 2 c bus operation (400khz maximum). without i 2 c wait cycles, the dap performs i 2 c operations. general i 2 c operation the i 2 c bus uses sda (data) and scl (clock) to communicate between integrated circuits in a system. data is transferred on the bus serially one bit at a time. with the most significant bit (msb) transferred first, the address and data can be transferred in byte (8bit) format. in addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. the bus uses transitions on the sda when the clock is high to indicate start and stop conditions. a high-to-low transition on sda indicates a start, and a low-to-high transition indicates a stop. normal data bit transitions must occur within the low time of the clock. these conditions are shown in figure 10. the master generates the 7bit slave address and the read/write (r/w) bit to open communication with another device and then waits for an acknowledge condition. the apa3160 holds sda low during the acknowledge clock to indicate an acknowledgment. when this occurs, the master transmits the next byte of the sequence. each device is addressed by a unique 7bit slave address plus r/w bit (1 byte). all compatible devices share the same signals via a bidirectional bus using a wired-and connection. an external pull-up resistor must be used for the sda and scl signals to set the high level for the bus. f i g u r e 1 0 . t y p i c a l i 2 c s e q u e n c e 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7-bit slave address r/ w a 8-bit register address (n) 8-bit register data for address (n) a a a 8-bit register data for address (n) sda scl start stop there is no limit on the number of bytes that can be transmitted between start and stop conditions. when the last word transfers, the master generates a stop condition to release the bus. a generic data transfer sequence is shown in figure 10. the 7bit address for apa3160 is 0011 010 (0x34). apa3160 address can be changed from 0x34 to 0x38 by writing 0x38 to device address register 0xf9. c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 6 a p a 3 1 6 0 single- and multiple-byte transfers f u n c t i o n d e s c r i p t i o n ( c o n t . ) the serial control interface supports single-byte and multiple-byte (r/w) operations for sub-addresses 0x00 to 0x1f. however, for the sub-addresses 0x20 to 0xff, the serial control interface supports only multiple-byte read/write operations (in multiples of 4 bytes). during multiple-byte read operations, the dap responds with data, a byte at a time, starting at the sub-address assigned, as long as the master device continues to respond with acknowledges. if a particular sub-address does not contain 32 bits, the unused bits are read as logic 0. during multiple-byte write operations, the dap compares the number of bytes transmitted to the number of bytes that are required for each specific sub-address. supplying a sub-address for each sub-address transaction is referred to as random i 2 c addressing. the apa3160 also supports sequential i 2 c addressing. for write transactions, if a sub-address is issued and followed by data for that sub-address and the 15 sub-addresses that follow, a sequential i 2 c write transaction has taken place, and the data for all 16 sub-addresses is successfully received by the apa3160. for i 2 c sequential write transactions, the sub- address then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many sub-addresses are written. as was true for random addressing, sequential addressing requires that a complete set of data be transmitted. if only a partial set of data is written to the last sub- address, the data for the last sub-address is discarded. however, if all other data written is accepted, only the incomplete data is discarded. single-byte write as shown in figure 11, a single-byte data write transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the r/w bit. the r/w bit determines the direction of the data transfer. for a write data transfer, the r/w bit will be a 0. after receiving the correct i 2 c device address and the r/w bit, the dap responds with an acknowledge bit. and then, the master transmits the address byte or bytes corresponding to the apa3160 internal memory address being accessed. after receiving the address byte, the apa3160 responds with an acknowl- edge bit again. next, the master device transmits the data byte to be written to the memory address being accessed. after receiving the data byte, the apa3160 again responds with an acknowledge bit. finally, the master device trans- mits a stop condition to complete the single-byte data write transfer. a6 a5 a4 a3 a2 a1 a0 ack r/w a6 a5 a4 a3 a2 a1 a0 ack a7 d6 d5 d4 d3 d2 d1 d0 ack d7 start condition stop condition i 2 c device address and read/ write bit sub-address data byte acknowledge acknowledge acknowledge f i g u r e 1 1 . s i n g l e - b y t e w r i t e t r a n s f e r c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 7 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) multiple-byte write a multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the dap as shown in figure 12. after receiving each data byte, the apa3160 responds with an acknowledge bit. a6 a5 a1 a0 ack r/w a6 a2 a1 a0 ack a7 d0 ack d7 start condition stop condition i 2 c device address and read/ write bit sub-address first data byte acknowledge acknowledge acknowledge d0 ack acknowledge d7 acknowledge d0 ack d7 last data byte other data bytes f i g u r e 1 2 . m u l t i p l e - b y t e w r i t e t r a n s f e r single-byte read as shown in figure 13, a single-byte data read transfer begins with the master device transmitting a start condition followed by the i 2 c device address and the r/w bit. for the data read transfer, both a write followed by a read are actually done. initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. as a result, the r/w bit becomes a 0. after receiving the apa3160 address and the read/write bit, apa3160 responds with an acknowledge bit. besides, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the apa3160 address and the read/write bit again. this time the read/ write bit becomes a 1, indicating a read transfer. after receiving the address and the read/write bit, the apa3160 again responds with an acknowledge bit. and then, the apa3160 transmits the data byte from the memory address being read. after receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. f i g u r e 1 3 . s i n g l e - b y t e r e a d t r a n s f e r multiple-byte read a multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the apa3160 to the master device as shown in figure 14. except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. f i g u r e 1 4 . m u l t i p l e - b y t e r e a d t r a n s f e r a6 a0 ack r/w a6 a1 a0 ack a7 start condition i 2 c device address and read/ write bit sub- address acknowledge acknowledge a6 a0 r/w i 2 c device address and read/ write bit ack acknowledge repeat start condition d0 ack d7 stop condition first data byte acknowledge d0 ack not acknowledge d7 acknowledge d0 ack d7 last data byte other data bytes a6 a5 a1 a0 ack r/w a6 a1 a0 ack a7 start condition stop condition i 2 c device address and read/ write bit sub-address acknowledge acknowledge a6 a5 a1 a0 r/w i 2 c device address and read/ write bit ack d6 d1 d0 ack d7 data byte acknowledge not acknowledge repeat start condition c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 8 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) dynamic range control (drc) the drc scheme has a single threshold, offset, and slope (all programmable). there is one ganged drc for the left/ right channels. the drc input/output diagram is shown in figure 15. p r o f e s s i o n a l - q u a l i t y d y n a m i c r a n g e c o m p r e s s i o n a u t o m a t i c a l l y a d - j u s t s v o l u m e t o f l a t t e n v o l u m e l e v e l . ? o n e d r c f o r l e f t / r i g h t . ? t h e d r c h a s a d j u s t a b l e t h r e s h o l d , o f f s e t , a n d c o m p r e s s i o n l e v e l s . ? p r o g r a m m a b l e e n e r g y , a t t a c k , a n d d e c a y t i m e c o n s t a n t s . ? t r a n s p a r e n t c o m p r e s s i o n : c o m p r e s s o r s c a n a t t a c k f a s t e n o u g h t o a v o i d a p p a r e n t c l i p p i n g b e f o r e e n g a g i n g , a n d d e c a y t i m e s c a n b e s e t s l o w e n o u g h t o a v o i d p u m p i n g . f i g u r e 1 5 . d y n a m i c r a n g e c o n t r o l t input level (db) o u t p u t l e v e l ( d b ) k o 1:1 transfer function implemented transfer function energy filter compression control attack and decay filters a, w t, k, o a a , w a /a d , w d 0x3b/0x3c 0x40,0x41,0x42 0x3a drc audio input drc coefficient s z -1 a w alpha filter structure note : w =1- a f i g u r e 1 6 . d r c s t r u c t u r e biquad structure all biquads use a 2nd order iir filter structure as shown below. each biquad has 3 coefficients on the direct path (b0, b1, b2) and 2 coefficients on feedback path (a1 and a2) which is shown in the diagram. s z -1 z -1 z -1 z -1 magnitude trunction x(n) y(n) b 0 b 1 b 2 a 1 a 2 f i g u r e 1 7 . b i q u a d f i l t e r c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 1 9 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) 26bit 3.23 number format all mixer gain coefficients are 26 bit coefficients and use a 3.23 number format. numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. this is shown in figure 18. f i g u r e 1 8 . 3 . 2 3 f o r m a t the decimal value of a 3.23 format number can be found by following the weighting and is shown in figure 18. if the msb is logic 0, the number is a positive number, and the weighting shown yields the correct number. if the msb is a logic 1, and then the number is a negative number. in this case, every bit must be inverted, a 1 added to the result, and then the weighting shown in figure 19 applied to obtain the magnitude of the negative number. f i g u r e 1 9 . c o n v e r s i o n w e i g h t i n g f a c r o e s 3 . 2 3 f o r m a t t o f l o a t i n g p o i n t gain coefficients, entered via the i 2 c bus, must be entered as 32 bit binary numbers. the format of the 32 bit number (4 byte or 8 digit hexadecimal number) is shown in figure 20. f i g u r e 2 0 . a l i g n m e n t o f 3 . 2 3 c o e f f i c i e n t i n 3 2 b i t i 2 c w o r d 2 -23 bit 2 0 bit 2 1 bit 2 -1 bit 2 -4 bit (1 or 0) x2 1 + (1 or 0) x2 0 + (1 or 0) x2 -1 + (1 or 0) x2 -4 + (1 or 0) x2 -23 s_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx 2 -23 bit 2 -5 bit 2 -1 bit 2 0 bit 2 1 bit sign bit u u u u u u s x x x x x x x x x x x x x x x x x x x x x x x x 0 fraction digit 6 fraction digit 5 fraction digit 4 fraction digit 2 fraction digit 3 fraction digit 1 integer digit 1 sign bit coefficient digit 8 coefficient digit 7 coefficient digit 6 coefficient digit 5 coefficient digit 4 coefficient digit 3 coefficient digit 2 coefficient digit 1 x c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 0 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sample calculation for 3.23 format d b linear decimal hex (3.23 format) 0 1 8388608 00800000 5 1.7782794 14917288 00e39ea8 - 5 0.5623413 4717260 0047facc x l = 10 (x/20) d = 8388608 l h = dec2hex (d, 8) sample calculation for 9.17 format db linear decimal hex ( 9 . 17 format) 0 1 131072 00 02 0000 5 1.7782794 233082.6 00 0 3 8 e 7 a - 5 0.5623413 73707.2 00 011feb x l = 10 (x/20) d = 131072 l h = dec2hex (d, 8) recommended use model f i g u r e 2 1 . r e c o m m e n d e d c o m m a n d s e q u e n c e avdd/dvdd sd mclk lrclk sclk sdin i 2 s scl sda i 2 c rst pvdd/avcc trim dap config other config exit sd volume and mute commands clock errors and rate changes ok enter sd stable and valid clocks stable and valid clocks 3v t entersd t autodetect t por t por t exitsd t vdd-pvccl 10v 7.5v 10v 7.5v t rl-pvcch t pvccl-vddh t vddh-dl 3v reconfigure dap after shutdown reconfigure dap after shutdown normal operation shutdown power down t dl-vddh t rl-dv intialization t rh-i2c t dv-rh t pvcch-i2c t autodetect c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 1 a p a 3 1 6 0 recommended use model (cont.) f u n c t i o n d e s c r i p t i o n ( c o n t . ) apa3160 parameter description min. typ. max. unit t vddh - dl time digital inputs must remain low after avdd/dvdd goes above 3v 0 - - t dl - vddh time digital inputs must be low before avdd/dvdd goes below 3v 0 - - t vddh - pv dd l time pv dd /avcc remains below 7.5v after avdd/dvdd goes above 3v 100 - - t pv dd l - vddh time pv dd /avcc must be below 7.5v before avdd/dvdd goes below 3v 0 - - t pv dd h - i2c time pv dd /avcc must be above 10v before i 2 c commands may address device 10 - - t rl - pv dd h time pv dd /avcc must remain above 10v after rst goes low 2 - - m s t rh - i2c time reset must be high before i 2 c commands may address device 13.5 - - ms t dv - rh time digital inputs must be valid (driven as recommended) before rst goes high 100 - - t rl - dv time digital inputs must remain valid (driven as recommended) after rst goes low 2 - - m s t autodetect auto - detect completion wait time (given stable and valid clocks) before issuing further commands 50 - - t exitsd exit shutdown wait time bef ore issuing further commands to device (t start given by register 0x1a) 1+1.3 x t start - - t entersd enter shutdown wait time before issuing further commands to device (t stop given by register 0x1a) 1+1.3 x t stop - - t por power - on - reset wait time after 1st trim following avdd/dvdd power - up (t start given by register 0x1a) (does not apply to trim commands following subsequent resets) 240 + 1.3 x t start - - ms f i g u r e 2 2 . p o w e r l o s s s e q u e n c e 3v 10v 7.5v t rl-pvcch t pvccl-vddh avdd/dvdd sd mclk lrclk sclk sdin i 2 s scl sda i 2 c rst pvdd/avcc t pl-hl t dl-vddh sudden power loss (bd) c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 2 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) apa3160 parameter description min. typ. max. unit t r l - d v time digital inputs must remain valid (driven as recommended) after rst goes low 2 - - t dl - vddh time digital inputs must be low before avdd/dvdd goes below 3v 0 - - t r l - pv dd h time pv dd /a vcc must remain above 10v after rst goes low 2 - - t pvddl - v dd h time pv dd /avcc must be below 7.5v before avdd/dvdd goes below 3v 0 - - m s recommended use model (cont.) recommended command sequences the dap has two groups of commands. one set is for configuration and is intended for use only during initialization. the other set has built-in click and pop protection and may be used during normal operation while audio is streaming. the following supported command sequences illustrate how to initialize, operate, and shutdown the device. initialization sequence u s e t h e f o l l o w i n g s e q u e n c e t o p o w e r - u p a n d i n i t i a l i z e t h e d e v i c e : 1 . h o l d a l l d i g i t a l i n p u t s l o w a n d r a m p u p a v d d / d v d d t o a t l e a s t 3 v . 2 . i n i t i a l i z e d i g i t a l i n p u t s a n d p v d d s u p p l y a s f o l l o w s : ? d r i v e r s t = 0 , s d = 1 , a n d o t h e r d i g i t a l i n p u t s t o t h e i r d e s i r e d s t a t e w h i l e e n s u r i n g t h a t a l l a r e n e v e r m o r e t h a n 2 . 5 v a b o v e a v d d / d v d d . p r o v i d e s t a b l e a n d v a l i d i 2 s c l o c k s ( m c l k , l r c l k , a n d s c l k ) . w a i t a t l e a s t 1 0 0 m s , d r i v e r s t = 1 , a n d w a i t a t l e a s t a n o t h e r 1 3 . 5 m s . ? r a m p u p p v d d t o a t l e a s t 8 v w h i l e e n s u r i n g t h a t i t r e m a i n s b e l o w 6 v f o r a t l e a s t 1 0 0 m s a f t e r a v d d / d v d d r e a c h e s 3 v . t h e n w a i t a t l e a s t a n o t h e r 1 0 m s . 3 . c o n f i g u r e t h e d a p v i a i 2 c ( s e e u s e r s ? s g u i d e f o r t y p i c a l v a l u e s ) : b i q u a d s ( 0 x 2 9 - 3 6 ) d r c p a r a m e t e r s ( 0 x 3 a - 3 c , 0 x 4 0 - 4 2 , a n d 0 x 4 6 ) b a n k s e l e c t ( 0 x 5 0 ) . 4 . c o n f i g u r e r e m a i n i n g r e g i s t e r s . 5 . e x i t s h u t d o w n ( s e q u e n c e d e f i n e d b e l o w ) . normal operation the following are the only events supported during normal operation: (a) writes to master/channel volume registers (b) writes to soft mute register (c) enter and exit shutdown (sequence defined below) (d) clock errors and rate changes n o t e : e v e n t s ( c ) a n d ( d ) a r e n o t s u p p o r t e d f o r 2 4 0 m s + 1 . 3 x t 0 0 a f t e r t r i m f o l l o w i n g a v d d / d v d d p o w e r u p r a m p ( w h e r e t s t a r t i s s p e c i f i e d b y r e g i s t e r 0 x 1 a ) . c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 3 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) shutdown sequence e n t e r : 1 . e n s u r e i 2 s c l o c k s h a v e b e e n s t a b l e a n d v a l i d f o r a t l e a s t 5 0 m s . 2 . w r i t e 0 x 4 0 t o r e g i s t e r 0 x 0 5 . 3 . w a i t a t l e a s t 1 m s + 1 . 3 x t s t o p ( w h e r e t s t o p i s s p e c i f i e d b y r e g i s t e r 0 x 1 a ) . 4 . o n c e i n s h u t d o w n , s t a b l e c l o c k s a r e n o t r e q u i r e d w h i l e d e v i c e r e m a i n s i d l e . 5 . i f d e s i r e d , r e c o n f i g u r e b y e n s u r i n g t h a t c l o c k s h a v e b e e n s t a b l e a n d v a l i d f o r a t l e a s t 5 0 m s b e f o r e r e t u r n i n g t o s t e p 4 o f i n i t i a l i z a t i o n s e q u e n c e . e x i t : 1 . e n s u r e i 2 s c l o c k s h a v e b e e n s t a b l e a n d v a l i d f o r a t l e a s t 5 0 m s . 2 . w r i t e 0 x 0 0 t o r e g i s t e r 0 x 0 5 ( e x i t s h u t d o w n c o m m a n d m a y n o t b e s e r v i c e d f o r a s m u c h a s 2 4 0 m s a f t e r t r i m f o l l o w i n g a v d d / d v d d p o w e r u p r a m p ) . 3 . w a i t a t l e a s t 1 m s + 1 . 3 x t s t a r t ( w h e r e t s t a r t i s s p e c i f i e d b y r e g i s t e r 0 x 1 a ) . 4 . p r o c e e d w i t h n o r m a l o p e r a t i o n . power-down sequence use the following sequence to power-down the device and its supplies: 1. if time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert sd=0 and wait at least 2ms. 2. assert rst=0. 3. drive digital inputs low and ramp down pvdd supply as follows: ? drive all digital inputs low after rst has been low for at least 2 m s. ? ramp down pvdd while ensuring that it remains above 8v until rst has been low for at least 2 m s. 4. ramp down avdd/dvdd while ensuring that it remains above 3v until pvdd is below 6v and that it is never more than 2.5v below the digital inputs. sub a ddress register name no. of bytes contents initialization values a u indicates unused bits. 0x00 clock control register 1 description shown in subsequent section 0x6c 0x01 device id register 1 description shown in subsequent section 0x 00 0x02 error status register 1 description shown in subsequent section 0x00 0x03 system control register 1 1 description shown in subsequent section 0x 80 0x04 serial data interface 1 description shown in subsequent section 0x05 0x05 1 description shown in sub sequent section 0x 40 0x06 soft mute register 1 description shown in subsequent section 0x00 0x07 master volume 1 description shown in subsequent section 0xff (mute) 0x08 channel 1 vol 1 description shown in subsequent section 0x30 (0db) 0x09 channel 2 vol 1 description shown in subsequent section 0x30 (0db) 0x0a fine master volume 1 description shown in subsequent section 0x00 (0db) 0x0b - 0x0d reserved ( 1 ) 0x0e volume configuration register 1 description shown in subsequent section 0x91 table 1. serial control interface register summary c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 4 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sub a ddress register name no. of bytes contents initialization values 0x0f 1 reserved ( 1 ) 0x10 modulation limit register 1 description shown in subsequent section 0x02 0x15 - 0x19 1 reserved ( 1 ) 0x1a start/stop period register 1 description show n in subsequent section 0x0a 0x1b 1 reserved ( 1 ) 0x1c 1 reserved ( 1 ) 0x1d ? 0x1f 1 reserved ( 1 ) 0x20 input mux register 4 description shown in subsequent section 0x 0089 777a 0x21 - 0x24 4 reserved ( 1 ) 0x25 pwm mux register 4 description shown in subsequent section 0x0102 1345 0x26 - 0x28 4 reserved ( 1 ) u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x29 ch1_bq [0] 20 u [31:26], a2 [2 5:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2 a ch1_bq [1] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2 b ch1_bq [ 2 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x00 00 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2 c ch1_bq [ 3 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2 d ch1_bq [ 4 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 0x2 e ch1_bq [ 5 ] 20 u [31:26], b1 [25:0] 0x0000 0000 table 1. serial control interface register summary (cont.) c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 5 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sub a ddress register name no. of bytes contents initialization values u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2 e ch1_bq [ 5 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x2 f ch1_bq [ 6 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b 2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x 30 ch1_bq [ 0 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x00 00 0000 0x 31 ch1_bq [ 1 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x 32 ch1_bq [ 2 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x 33 ch1_bq [ 3 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x 34 ch1_bq [ 4 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 0x 35 ch1_bq [ 5 ] 20 u [31:26], a1 [25:0] 0x0000 0000 table 1. serial control interface register summary (cont.) c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 6 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) sub a ddress register name no. of bytes contents initialization values 0x 35 ch1_bq [ 5 ] 20 u [31:26], a2 [25:0] 0x0000 0000 u [31:26], b0 [25:0] 0x0080 0000 u [31:26], b1 [25:0] 0x0000 0000 u [31:26], b2 [25:0] 0x0000 0000 u [31:26], a1 [25:0] 0x0000 0000 0x 36 ch1_bq [ 6 ] 20 u [31:26], a2 [25:0] 0x0000 0000 0x37~ 0x39 reserved ( 2 ) drc ae ( 3 ) u [31:26], ae [25:0] 0x0080 0000 0x3a drc (1 - ae) 8 u [31:26], (1 - ae) [25:0] 0x0000 0000 drc aa u [31:26], aa [25:0] 0x0080 000 0 0x3b drc (1 - aa) 8 u [31:26], (1 - aa) [25:0] 0x0000 0000 drc ad u [31:26], ad [25:0] 0x0080 0000 0x3c drc (1 - ad) 8 u [31:26], (1 - ad) [25:0] 0x0000 0000 0x3d ~0x3f reserved (2) 0x40 drc - t 4 t [31:0] (9.23 format) 0x007f ffff 0x41 drc - k 4 u [ 31:26], k [25:0] 0x0080 000 0x42 drc - o 4 u [31:26], o [25:0] 0x0080 0000 0x43 - 0x45 reserved (2) 0x46 drc control 4 description shown in subsequent section 0x0000 0000 0x47 - 0x4f reserved (2) 0x50 eq control reserved (2) 0x0f70 8000 0x51 - 0xf8 reserved (2) 0xf9 update device address 4 u [31:8], new dev id[7:0] (new dev id=0x38) 0x00000034 0xfa - 0xff reserved (2) table 1. serial control interface register summary (cont.) n o t e ( 1 ) : r e s e r v e d r e g i s t e r s h o u l d n o t b e a c c e s s e d . n o t e ( 2 ) : r e s e r v e d r e g i s t e r s h o u l d n o t b e a c c e s s e d . n o t e ( 3 ) : ? a e ? s t a n d s f o r a o f e n e r g y f i l t e r , ? a a ? s t a n d s f o r a o f a t t a c k f i l t e r a n d ? a d ? s t a n d s f o r a o f d e c a y f i l t e r a n d 1 - a = w . c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 7 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) clock control register (0x00) the clocks and data rates are automatically determined by the apa3160. the clock control register contains the auto- detected clock status. bits d7-d5 reflect the sample rate. bits d4-d2 reflect the mclk frequency. d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 - - - - - f s =32khz sample rate 0 0 1 - - - - - reserved (4) 0 1 0 - - - - - reserved ( 4 ) 0 1 1 - - - - - f s =44.1/48khz sample rate ( 5 ) 1 0 0 - - - - - f s =16khz sample rate 1 0 1 - - - - - f s =22.05/24khz sample r ate 1 1 0 - - - - - f s =8khz sample rate 1 1 1 - - - - - f s =11.025/12khz sample rate - - - 0 0 0 - - mclk frequency=64 xf s ( 6 ) - - - 0 0 1 - - mclk frequency= 128xf s ( 6 ) - - - 0 1 0 - - mclk frequency= 192xf s ( 7 ) - - - 0 1 1 - - mclk frequency= 256xf s ( 5 ) ( 8 ) - - - 1 0 0 - - mclk frequency= 384xf s - - - 1 0 1 - - mclk frequency= 512xf s - - - 1 1 0 - - reserved ( 4 ) - - - 1 1 1 - - reserved ( 4 ) - - - - - - 0 - reserved (4) - - - - - - - 0 reserved (4) t a b l e 2 . c l o c k c o n t r o l r e g i s t e r ( 0 x 0 0 ) n o t e ( 4 ) : r e s e r v e d r e g i s t e r s s h o u l d n o t b e a c c e s s e d . n o t e ( 5 ) : i t a l i c i s d e f a u l t . n o t e ( 6 ) : o n l y a v a i l a b l e f o r 4 4 . 1 k h z a n d 4 8 k h z r a t e s . n o t e ( 7 ) : r a t e o n l y a v a i l a b l e f o r 3 2 / 4 4 . 1 / 4 8 k h z s a m p l e r a t e s . n o t e ( 8 ) : n o t a v a i l a b l e a t 8 k h z . device id register (0x01) the device id register contains the id code for the firmware revision. d7 d6 d5 d4 d3 d2 d1 d0 function x - - - - - - - reserved - 0 0 0 0 0 0 0 identification code t a b l e 3 . g e n e r a l s t a t u s r e g i s t e r ( 0 x 0 1 ) n o t e : i t a l i c i s d e f a u l t . c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 8 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) error status register (0x02) t h e e r r o r b i t s a r e s t i c k y a n d a r e n o t c l e a r e d b y t h e h a r d w a r e . t h i s m e a n s t h a t t h e s o f t w a r e m u s t c l e a r t h e r e g i s t e r ( w r i t e z e r o e s ) a n d t h e n r e a d t h e m t o d e t e r m i n e i f t h e y a r e p e r s i s t e n t e r r o r s . e r r o r d e f i n i t i o n s : m c l k e r r o r : m c l k f r e q u e n c y i s c h a n g i n g . t h e n u m b e r o f m c l k s p e r l r c l k i s c h a n g i n g . s c l k e r r o r : t h e n u m b e r o f s c l k s p e r l r c l k i s c h a n g i n g . l r c l k e r r o r : l r c l k f r e q u e n c y i s c h a n g i n g . t a b l e 4 . e r r o r s t a t u s r e g i s t e r ( 0 x 0 2 ) d7 d6 d5 d4 d3 d2 d1 d0 function 1 - - - - - - - mclk error - 1 - - - - - - pll auto clock error - - 1 - - - - - sclk error - - - 1 - - - - lrclk error - - - - 1 - - - reserved - - - - - 1 - - reserved - - - - - - 1 - over temperature warning (sets around 145 o c ) por error, ocp, thermal shutdown error 0 0 0 0 0 0 0 0 no errors system control register 1 (0x03) the system control register 1 has several functions: bit d7: if 0, the dc-blocking filter for each channel is disabled. if 1, the dc-blocking filter ( -3db cutoff < 1hz ) for each channel is enabled (default). bit d5: if 0, use soft unmute on recovery from clock error. this is a slow recovery. unmute takes same time as volume ramp defined in reg 0x0e. if 1, use hard unmute on recovery from clock error (default). this is a fast recovery, a single step volume ramp bits d1-d0: select de-emphasis. t a b l e 5 . s y s t e m c o n t r o l r e g i s t e r 1 ( 0 x 0 3 ) d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - pwm high - pass (dc blocking) dis enabled 1 - - - - - - - pwm high - pass (dc blocking) enabled - 0 - - - - - - reserved - - 0 - - - - - reserved - - 0 - - - - - reserved - - - 0 - - - - reserved - - - - 0 - - - reserved - - - - - 0 - - reserved - - - - - - 0 0 no de - emphasis - - - - - - 0 1 reserved - - - - - - 1 0 de - emphasis for f s =44.1khz - - - - - - 1 1 de - emphasis for f s =4 8 khz n o t e : i t a l i c i s d e f a u l t . n o t e : i t a l i c i s d e f a u l t . c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 2 9 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) serial data interface register (0x04) a s s h o w n i n t a b l e 6 , t h e a p a 3 1 6 0 s u p p o r t s 9 s e r i a l d a t a m o d e s . t h e d e f a u l t i s 2 4 b i t , i 2 s m o d e . table 6. serial data interface control register (0x04) format d7 d6 d5 d4 d3 d2 d1 d0 word length receive serial data interface format 0 0 0 0 0 0 0 0 16 right - justified 0 0 0 0 0 0 0 1 20 right - justified 0 0 0 0 0 0 1 0 24 right - justified 0 0 0 0 0 0 1 1 16 i 2 s 0 0 0 0 0 1 0 0 20 i 2 s 0 0 0 0 0 1 0 1 24 i 2 s 0 0 0 0 0 1 1 0 16 left - justified 0 0 0 0 0 1 1 1 20 left - justified 0 0 0 0 1 0 0 0 24 left - justified 0 0 0 0 1 - 1 0 - reserved 0 0 0 0 1 - - 1 - reserved 0 0 0 0 1 1 1 1 - reserved n o t e : i t a l i c i s d e f a u l t . system control register 2 (0x05) when bit d6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). t a b l e 7 . s y s t e m c o n t r o l r e g i s t e r 2 ( 0 x 0 5 ) d7 d6 d5 d4 d3 d2 d1 d0 function 0 - - - - - - - reserved - 1 - - - - - - enter all channel shut down (hard mute) - 0 - - - - - - exit all channel shut down (normal operation) - - 0 0 0 0 0 0 reserved n o t e : i t a l i c i s d e f a u l t . soft mute register (0x06) writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute). d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - - - 1 soft mute channel 1 - - - - - - - 0 soft un - mute channel 1 - - - - - - 1 - soft mute channel 2 - - - - - - 0 - soft un - mute channel 2 0 0 0 0 0 0 - - reserved t a b l e 8 . s o f t m u t e r e g i s t e r ( 0 x 0 6 ) n o t e : i t a l i c i s d e f a u l t . c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 0 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) volume registers (0x07, 0x08, 0x09) s t e p s i z e i s 0 . 5 d b . m a s t e r v o l u m e - 0 x 0 7 ( d e f a u l t i s m u t e ) c h a n n e l - 1 v o l u m e - 0 x 0 8 ( d e f a u l t i s 0 d b ) c h a n n e l - 2 v o l u m e - 0 x 0 9 ( d e f a u l t i s 0 d b ) t a b l e 9 . v o l u m e r e g i s t e r s ( 0 x 0 7 , 0 x 0 8 , 0 x 0 9 ) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 0 0 0 0 0 24db 0 0 1 1 0 0 0 0 0db 1 1 0 0 1 1 0 1 - 78.5db 1 1 0 0 1 1 1 0 - 7 9 . 0 db 1 1 0 0 1 1 1 1 values between 0xcf and 0xfe are reserved 1 1 1 1 1 1 1 1 mute (default for master volume) master fine volume register (0x0a) this register can be used to provide precision tuning of master volume. t a b l e 1 0 . m a s t e r f i n e v o l u m e r e g i s t e r ( 0 x 0 a ) d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - - 0 0 0db - - - - - - 0 1 0.125db - - - - - - 1 0 0.25db - - - - - - 1 1 0.345db 1 - - - - - - - write enable bit - - - - - - - - ignore write to register 0x0a volume configuration register (0x0e) bits volume slew rate (used to control volume change and mute ramp rates). these bits control the d2-d0: number of steps in a volume ramp. volume steps occur at a rate that depends on the sample rate of the i 2 s data as follows. sample rate (khz) approximate ramp rate 8/16/32 125 m s/step 11.025/22.05/44.1 90.7 m s/step 12/24/48 83.3 m s/step d7 d6 d5 d4 d3 d2 d1 d0 function 1 0 0 1 0 - - - reserved - - - - - 0 0 0 volume slew 512 steps (43ms volume ramp time at 48khz) t a b l e 1 1 . v o l u m e c o n t r o l r e g i s t e r ( 0 x 0 e ) n o t e : i t a l i c i s d e f a u l t . n o t e : i t a l i c i s d e f a u l t . c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 1 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) d7 d6 d5 d4 d3 d2 d1 d0 function - - - - - 0 0 1 volume slew 1024 steps (85ms volume ramp time at 48khz) - - - - - 0 1 0 volume slew 2048 steps (171ms volume ramp time at 48khz) - - - - - 0 1 1 volume slew 256 steps (21ms volume ramp time at 48khz) - - - - - 1 x x reserved t a b l e 1 1 . v o l u m e c o n t r o l r e g i s t e r ( 0 x 0 e ) n o t e : i t a l i c i s d e f a u l t . modulation limit register (0x10) t a b l e 1 2 . m o d u l a t i o n l i m i t r e g i s t e r ( 0 x 1 0 ) d7 d6 d5 d4 d3 d2 d1 d0 modulation limit - - - - - 0 0 0 reserved - - - - - 0 0 1 98.4% - - - - - 0 1 0 97.7% - - - - - 0 1 1 96.9% - - - - - 1 0 0 96.1% - - - - - 1 0 1 95.3% - - - - - 1 1 0 94.5% - - - - - 1 1 1 93.8% 0 0 0 0 0 - - - reserved n o t e : i t a l i c i s d e f a u l t . volume configuration register (0x0e) (cont.) start/stop period register (0x1a) this register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the sd state. this helps reduce pops and clicks at start-up and shutdown. the times are only approximate and vary depending on device activity level and i 2 s clock stability. t a b l e 1 3 . s t a r t / s t o p p e r i o d r e g i s t e r ( 0 x 1 a ) d7 d6 d5 d4 d3 d2 d1 d0 function 0 0 0 - - - - - reserved - - - 0 0 - - - no 50% duty cycle start/stop period - - - 0 1 0 0 0 16.5ms 50% duty cycle start/stop period - - - 0 1 0 0 1 23.9 ms 50% duty cycle start/stop period - - - 0 1 0 1 0 31.4 ms 50% du ty cycle start/stop period - - - 0 1 0 1 1 40.4 ms 50% duty cycle start/stop period - - - 0 1 1 0 0 53.9 ms 50% duty cycle start/stop period - - - 0 1 1 0 1 70.3 ms 50% duty cycle start/stop period - - - 0 1 1 1 0 94.2 ms 50% duty cycle start/stop period - - - 0 1 1 1 1 125.7 ms 50% duty cycle start/stop period c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 2 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) d7 d6 d5 d4 d3 d2 d1 d0 function - - - 1 0 0 0 0 164.6 ms 50% duty cycle start/stop period - - - 1 0 0 0 1 239.4 ms 50% duty cycle start/stop period - - - 1 0 0 1 0 314.2 ms 50% duty cycle start/stop period - - - 1 0 0 1 1 403.9 ms 50% duty cycle start/sto p period - - - 1 0 1 0 0 538.6 ms 50% duty cycle start/stop period - - - 1 0 1 0 1 703.4 ms 50% duty cycle start/stop period - - - 1 0 1 1 0 942.5 ms 50% duty cycle start/stop period - - - 1 0 1 1 1 1256.6 ms 50% duty cycle start/stop period - - - 1 1 0 0 0 1728.1 ms 50% duty cycle start/stop period - - - 1 1 0 0 1 2513.6 ms 50% duty cycle start/stop period - - - 1 1 0 1 0 3299.1 ms 50% duty cycle start/stop period - - - 1 1 0 1 1 4241.7 ms 50% duty cycle start/stop period - - - 1 1 1 0 0 5655.6 ms 50% duty cycle start/stop period - - - 1 1 1 0 1 7383.7 ms 50% duty cycle start/stop period - - - 1 1 1 1 0 9897.3 ms 50% duty cycle start/stop period - - - 1 1 1 1 0 13196.4 ms 50% duty cycle start/stop period start/stop period register (0x1a) (cont.) t a b l e 1 3 . s t a r t / s t o p p e r i o d r e g i s t e r ( 0 x 1 a ) n o t e : i t a l i c i s d e f a u l t . input multiplexer register (0x20) this register controls the modulation scheme (bd mode) as well as the routing of i 2 s audio to the internal channels. t a b l e 1 4 . i n p u t m u l t i p l e x e r r e g i s t e r ( 0 x 2 0 ) d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 function 0 0 0 0 0 0 0 0 reserved d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function 0 - - - - - - - reserved 1 - - - - - - - channel 1 bd mode - 0 0 0 - - - - sdin - l to channel 1 - 0 0 1 - - - - sdin - r to channel 1 - 0 1 0 - - - - reserved - 0 1 1 - - - - reserved - 1 0 0 - - - - reserved - 1 0 1 - - - - reserved - 1 1 0 - - - - ground (0) to channel 1 - 1 1 1 - - - - reserved - - - - 0 - - - reserved - - - - 1 - - - channel - 2 bd mode c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 3 a p a 3 1 6 0 d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function - - - - - 0 0 0 sdin - l to channel 2 - - - - - 0 0 1 sdin - r to channel 2 - - - - - 0 1 0 reserved - - - - - 0 1 1 reserved - - - - - 1 0 0 reserved - - - - - 1 0 1 reserved - - - - - 1 1 0 ground (0) to chann el 2 - - - - - 1 1 1 reserved d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 function 0 1 1 1 0 1 1 1 reserved d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function 0 1 1 1 0 0 1 0 reserved f u n c t i o n d e s c r i p t i o n ( c o n t . ) input multiplexer register (0x20) (cont.) t a b l e 1 4 . i n p u t m u l t i p l e x e r r e g i s t e r ( 0 x 2 0 ) n o t e : i t a l i c i s d e f a u l t . pwm output mux register (0x25) this dap output mux selects which internal pwm channel is output to the external pins. any channel can be output to any external output pin. bits d21-d20: selects which pwm channel is output to out_a bits d17-d16: selects which pwm channel is output to out_b bits d13-d12: selects which pwm channel is output to out_c bits d09-d08: selects which pwm channel is output to out_d note that channels are enclosed so that channel 1=0x00, channel 2=0x01, channel 1=0x02, and channel 2=0x03. t a b l e 1 5 . p w m o u t p u t m u x r e g i s t e r ( 0 x 2 5 ) d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 function 0 0 0 0 0 0 0 0 reserved d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function 0 0 - - - - - - reserved - - 0 0 - - - - multiplex channel 1 to out_a - - 0 1 - - - - multiplex channel 2 to out_a - - 1 0 - - - - multiplex channel 1 to out_a - - 1 1 - - - - multiplex channel 2 to out_a - - - - 0 0 - - reserved - - - - - - 0 0 multiplex channel 1 to out_b - - - - - - 0 1 multiplex channel 2 to out_b - - - - - - 1 0 multiplex channel 1 to out_b c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 4 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) pwm output mux register (0x25) (cont.) t a b l e 1 5 . p w m o u t p u t m u x r e g i s t e r ( 0 x 2 5 ) d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function - - - - - - 1 1 multiplex channel 2 to out_b d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 function 0 0 - - - - - - reserved - - 0 0 - - - - multiplex channel 1 to out_c - - 0 1 - - - - multiplex channel 2 to out_c - - 1 0 - - - - multiplex channel 1 to out_c - - 1 1 - - - - multiplex channel 2 to out_c - - - - 0 0 - - reserved - - - - - - 0 0 multiplex channel 1 to out_d - - - - - - 0 1 multiplex channel 2 to out_d - - - - - - 1 0 multiplex channel 1 to out_d - - - - - - 1 1 multiplex channel 2 to out_d d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function 0 1 0 0 0 1 0 1 reserved n o t e : i t a l i c i s d e f a u l t . d r c c o n t r o l ( 0 x 4 6 ) d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 function 0 0 0 0 0 0 0 0 reserved d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 function 0 0 0 0 0 0 0 0 reserved d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 function 0 0 0 0 0 0 0 0 reserved d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 function - - - - - - - 0 drc turned off - - - - - - - 1 drc turned on 0 0 0 0 0 0 0 - reserved n o t e : i t a l i c i s d e f a u l t . c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 5 a p a 3 1 6 0 f u n c t i o n d e s c r i p t i o n ( c o n t . ) fault description error 0 over - c urrent (oc) or u nder - v oltage (uvp) or o ver - t emperature (ot p ) 1 no faults (normal operation) o v e r - c u r r e n t ( o c ) p r o t e c t i o n w i t h c u r r e n t - l i m i t i n g t h e d e v i c e h a s i n d e p e n d e n t , f a s t - r e a c t i n g c u r r e n t d e t e c t o r s o n a l l h i g h - s i d e a n d l o w - s i d e p o w e r - s t a g e f e t s . t h e d e t e c t o r o u t p u t s a r e c l o s e l y m o n i t o r e d b y t w o p r o t e c t i o n s y s t e m s . t h e f i r s t p r o t e c t i o n s y s t e m c o n t r o l s t h e p o w e r s t a g e i n o r d e r t o p r e v e n t t h e o u t p u t c u r r e n t f u r t h e r i n c r e a s i n g , i . e . , i t p e r f o r m s a c y c l e - b y - c y c l e c u r r e n t - l i m i t i n g f u n c t i o n , r a t h e r t h a n p r e m a t u r e l y s h u t t i n g d o w n d u r i n g c o m b i n a t i o n s o f h i g h - l e v e l m u s i c t r a n s i e n t s a n d e x t r e m e s p e a k e r l o a d i m p e d a n c e d r o p s . i f t h e h i g h - c u r r e n t c o n d i t i o n s i t u a t i o n p e r s i s t s , i . e . , t h e p o w e r s t a g e i s b e i n g o v e r l o a d e d , a s e c o n d p r o t e c t i o n s y s t e m t r i g g e r s a l a t c h i n g s h u t d o w n , r e s u l t i n g i n t h e p o w e r s t a g e b e i n g s e t i n t h e h i g h - i m p e d a n c e ( h i - z ) s t a t e . t h e d e v i c e r e t u r n s t o n o r m a l o p e r a t i o n o n c e t h e f a u l t c o n d i t i o n ( i . e . , a s h o r t c i r c u i t o n t h e o u t p u t ) i s r e m o v e d . c u r r e n t l i m i t i n g a n d o v e r c u r r e n t p r o t e c t i o n a r e n o t i n d e p e n d e n t f o r h a l f - b r i d g e s . t h a t i s , i f t h e b r i d g e - t i e d l o a d b e t w e e n h a l f - b r i d g e s a a n d b c a u s e s a n o v e r c u r r e n t f a u l t , h a l f - b r i d g e s a , b , c , a n d d a r e s h u t d o w n . o v e r - t e m p e r a t u r e p r o t e c t i o n t h e a p a 3 1 6 0 h a s o v e r - t e m p e r a t u r e p r o t e c t i o n s y s t e m . i f t h e d e v i c e j u n c t i o n t e m p e r a t u r e e x c e e d s 1 5 0 c ( n o m i n a l ) , t h e d e v i c e i s p u t i n t o t h e r m a l s h u t d o w n , r e s u l t i n g i n a l l h a l f - b r i d g e o u t p u t s b e i n g s e t i n t h e h i g h - i m p e d a n c e ( h i - z ) s t a t e a n d f a u l t b e i n g a s s e r t e d l o w . t h e a p a 3 1 6 0 r e c o v e r s a u t o m a t i c a l l y o n c e t h e t e m p e r a t u r e d r o p s a p p r o x i m a t e l y 3 0 . u n d e r - v o l t a g e p r o t e c t i o n ( u v p ) a n d p o w e r - o n - r e s e t ( p o r ) t h e u v p a n d p o r c i r c u i t s o f t h e a p a 3 1 6 0 f u l l y p r o t e c t t h e d e v i c e i n a n y p o w e r - u p / d o w n a n d b r o w n o u t s i t u a t i o n . w h i l e p o w e r i n g u p , t h e p o r c i r c u i t r e s e t s t h e o v e r l o a d c i r c u i t ( o l p ) a n d e n s u r e s t h a t a l l c i r c u i t s a r e f u l l y o p e r a t i o n a l w h e n t h e p v d d a n d a v d d s u p p l y v o l t a g e s r e a c h 7 . 6 v a n d 2 . 7 v , r e s p e c t i v e l y . a l t h o u g h p v d d a n d a v d d a r e i n d e p e n - d e n t l y m o n i t o r e d , a s u p p l y v o l t a g e d r o p b e l o w t h e u v p t h r e s h o l d o n a v d d o r e i t h e r p v d d p i n r e s u l t s i n a l l h a l f - b r i d g e o u t p u t s i m m e d i a t e l y b e i n g s e t i n t h e h i g h - i m p e d a n c e ( h i - z ) s t a t e a n d e r r o r b e i n g a s s e r t e d l o w . e r r o r r e p o r t i n g a n y f a u l t r e s u l t i n g i n d e v i c e s h u t d o w n i s s i g n a l e d b y t h e e r r o r p i n g o i n g l o w ( s e e t a b l e 1 8 ) . a s t i c k y v e r s i o n o f t h i s p i n i s a v a i l a b l e o n d 1 o f r e g i s t e r 0 x 0 2 . t a b l e 1 6 . e r r o r o u t p u t s t a t e s c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 6 a p a 3 1 6 0 a p p l i c a t i o n i n f o r m a t i o n l a y o u t r e c o m m e n d a t i o n 4 a b s 9 a v s s 8 1 0 p l l _ l f 1 1 a v s s 5 g d r e g 6 n c 2 p v d d _ a 3 p v d d _ a 7 t m 1 1 2 2 v 5 _ a v 4 6 o u t _ b s c l k 2 1 t p 1 1 6 s d a 2 3 l r c l k 2 0 m c l k 1 5 s d i n 2 2 s c l 2 4 a v d d 1 3 s d 1 9 2 v 5 _ d v 1 8 e r r o r 1 4 t p 2 1 7 1 o u t _ a 4 5 p v d d _ b 4 0 p v d d _ c 4 7 p g n d _ a b 4 4 p v d d _ b 3 9 o u t _ c 4 8 p g n d _ a b 3 7 g n d _ c d 4 3 b b s 4 2 c b s 3 8 g n d _ c d 4 1 p v d d _ c d b s 3 3 d v s s 2 8 p v d d _ d 3 5 g d r e g 3 2 d v d d 2 7 p v d d _ d 3 4 o u t _ d 3 6 d v r e g 3 1 a g n d 3 0 t p 3 2 6 g n d 2 9 r s t 2 5 v dd v dd dv dd reset 470 o av dd scl av dd error flag master clock lrck sclk sdin 0 . 047 f 470 o 4700 pf sda v dd t m 2 avdd cap . & dvdd cap . should be close to the chip . power stage block , please use high voltage - bearing component . thermal pad should be soldered on ground plane of the pcb . pvdd cap . and bootstrap cap . should be close to the chip . output & vdd traces width = 4 0 mil , should be as short as they can , and symmetric . layout recommendation 4700 pf 0 . 047 f 1 f 0 . 033 f 0 . 1 f 220 f 2 2 . 1 k o 22 h 0 . 68 f 0 . 68 f 8 o 22 h 0 . 033 f 0 . 033 f 22 h 0 . 68 f 0 . 68 f 8 o 22 h 0 . 1 f 220 f 0 . 033 f 1 f 0 . 1 f 0 . 1 f 10 f 0 . 1 f 4 . 7 f 10 k o 18 . 2 k o 10 k o 0 . 1 f 10 f 0 o 0 . 1 f 0 . 1 f / pdn c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 7 a p a 3 1 6 0 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) l a y o u t r e c o m m e n d a t i o n 0 . 28 mm via diameter = 0 . 3 mm x 16 ground plane for thermalpad 1 . 7 mm 5 . 5 mm exposed for thermal pad connected 5 . 0 m m 0 . 5 mm tqfp 7 x 7 - 48 land pattern recommendation c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 8 a p a 3 1 6 0 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) l a y o u t r e c o m m e n d a t i o n pcb referance ( top layer ) c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 3 9 a p a 3 1 6 0 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) l a y o u t r e c o m m e n d a t i o n pcb referance ( bottom layer ) c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 0 a p a 3 1 6 0 p a c k a g e i n f o r m a t i o n t q f p 7 x 7 - 4 8 p 0 l 0 . 2 5 seating plane gauge plane l 0 . 006 0 o 7 o 0 o 7 o 0 . 50 bsc 0 . 020 bsc 0 . 45 0 . 75 0 . 018 0 . 030 s y m b o l min . max . 1 . 20 0 . 05 0 . 17 0 . 27 0 . 09 0 . 20 0 . 15 a a 1 b c d d 1 e e 1 e millimeters a 2 0 . 95 1 . 05 tqfp 7 x 7 - 48 p min . max . inches 0 . 047 0 . 002 0 . 037 0 . 041 0 . 007 0 . 011 0 . 004 0 . 008 d 2 e 2 3 . 00 0 . 118 3 . 00 5 . 50 5 . 50 0 . 177 0 . 118 0 . 177 8 . 80 9 . 20 0 . 346 0 . 362 6 . 90 7 . 10 0 . 272 0 . 280 8 . 80 6 . 90 7 . 10 9 . 20 0 . 346 0 . 272 0 . 362 0 . 280 note : 1 . followed from jedec ms - 026 abc . 2 . dimension " d 1 " and " e 1 " do not include mold protrusions . allowable protrusions is 0 . 25 mm per side . " d 1 " and " e 1 " are maximun plasticbody size dimensions including mold mismatch . d 1 d e 1 e e b d 2 e 2 exposed pad a 2 a 1 a c c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 1 a p a 3 1 6 0 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 16.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 16.0 ? 0.30 1.75 ? 0.10 7.5 ? 0.10 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tqfp7x7 - 48p 4.0 ? 0.10 12.0 ? 0.10 2.0 ? 0.10 1.5+0.10 - 0.00 1.5 min. 0.6+0.0 0 - 0.40 9.4 ? 0.20 9.4 ? 0.20 1.8 ? 0.20 (mm) c a r r i e r t a p e & r e e l d i m e n s i o n s d e v i c e s p e r u n i t package type unit quantity tqfp7x7 - 48p tape & reel 2500 h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 2 a p a 3 1 6 0 t a p i n g d i r e c t i o n i n f o r m a t i o n tqfp7x7-48p c l a s s i f i c a t i o n p r o f i l e user direction of feed c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 3 a p a 3 1 6 0 profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. c l a s s i f i c a t i o n r e f l o w p r o f i l e s table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c r e l i a b i l i t y t e s t p r o g r a m test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - j a n . , 2 0 1 3 w w w . a n p e c . c o m . t w 4 4 a p a 3 1 6 0 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8 |
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